[PATCH] D97316: AMDGPU: Add even aligned VGPR/AGPR register classes

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D97316#2582931 <https://reviews.llvm.org/D97316#2582931>, @arsenm wrote:

> In D97316#2582925 <https://reviews.llvm.org/D97316#2582925>, @rampitec wrote:
>
>> I do not think it will help. There will be the same issue as with reserved registers. Assume you have VReg_128_align2. For sure RA will allocate an aligned register. But something like coalescer will happily use sub1_sub2 on it and you will end up with an unaligned physreg at the end. To make this working you need to make sure these registers do not have unaligned subregs.
>
> This is already the case. The subregister indexes are considered unsupported by the class (e.g. getMatchingSuperRegClass and the composeSubReg* functions will fail)

Do you mean because to get a subreg a pass needs to query a subclass and aligned classes have only aligned subclasses? Are you sure there is no other way to get a subreg?


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