[llvm] d1b92c9 - [AMDGPU] Set threshold for regbanks reassign pass

[Stanislav Mekhanoshin via llvm-commits]

Author: Stanislav Mekhanoshin
Date: 2021-02-23T10:22:31-08:00
New Revision: d1b92c91afd0be8939bddbf04f55ec53cf29227a

URL: https://github.com/llvm/llvm-project/commit/d1b92c91afd0be8939bddbf04f55ec53cf29227a
DIFF: https://github.com/llvm/llvm-project/commit/d1b92c91afd0be8939bddbf04f55ec53cf29227a.diff

LOG: [AMDGPU] Set threshold for regbanks reassign pass

This is to limit compile time. I did experiments with some
inputs and found that compile time keeps reasonable for this
pass if we have less than 100000 virtual registers and then
starts to explode somewhere between 100000 and 150000.

Differential Revision: https://reviews.llvm.org/D97218

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp b/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
index 4fd76ba57ad2..137ac5466f4e 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
@@ -48,6 +48,11 @@ static cl::opt<unsigned> VerifyStallCycles("amdgpu-verify-regbanks-reassign",
   cl::value_desc("0|1|2"),
   cl::init(0), cl::Hidden);
 
+// Threshold to keep compile time reasonable.
+static cl::opt<unsigned> VRegThresh("amdgpu-regbanks-reassign-threshold",
+  cl::desc("Max number of vregs to run the regbanks reassign pass"),
+  cl::init(100000), cl::Hidden);
+
 #define DEBUG_TYPE "amdgpu-regbanks-reassign"
 
 #define NUM_VGPR_BANKS 4
@@ -807,6 +812,16 @@ bool GCNRegBankReassign::runOnMachineFunction(MachineFunction &MF) {
     return false;
 
   MRI = &MF.getRegInfo();
+
+  LLVM_DEBUG(dbgs() << "=== RegBanks reassign analysis on function " << MF.getName()
+                    << "\nNumVirtRegs = " << MRI->getNumVirtRegs() << "\n\n");
+
+  if (MRI->getNumVirtRegs() > VRegThresh) {
+    LLVM_DEBUG(dbgs() << "NumVirtRegs > " << VRegThresh
+                      << " threshold, skipping function.\n\n");
+    return false;
+  }
+
   TRI = ST->getRegisterInfo();
   MLI = &getAnalysis<MachineLoopInfo>();
   VRM = &getAnalysis<VirtRegMap>();
@@ -826,9 +841,6 @@ bool GCNRegBankReassign::runOnMachineFunction(MachineFunction &MF) {
                          AMDGPU::SReg_32RegClass.getNumRegs() / 2 + 1;
   RegsUsed.resize(NumRegBanks);
 
-  LLVM_DEBUG(dbgs() << "=== RegBanks reassign analysis on function " << MF.getName()
-               << '\n');
-
   unsigned StallCycles = collectCandidates(MF);
   NumStallsDetected += StallCycles;