[PATCH] D97192: [RISCV] Unify scalable- and fixed-vector EXTRACT_SUBVECTOR lowering

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll:27
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vslidedown.vi v25, v25, 6
+; CHECK-NEXT:    addi a0, zero, 2
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Based on a conversation with Andrew Waterman I had yesterday, the VL for the slidedown should just cover the elements we care about. Especially when the input LMUL > 1 and the output is LMUL <= 1. The smaller VL would allow the computation for the upper registers to be skipped. It still could be beneficial on CPUs with ALUs narrower than the VLEN.


Repository:
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  https://reviews.llvm.org/D97192/new/

https://reviews.llvm.org/D97192