[PATCH] D97192: [RISCV] Unify scalable- and fixed-vector EXTRACT_SUBVECTOR lowering

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck marked 2 inline comments as done.
frasercrmck added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll:27
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vslidedown.vi v25, v25, 6
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craig.topper wrote:
> Should we be using a VL of 8 here?
Hmm yes we should. Let me find it.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll:73
+; LMULMAX2-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; LMULMAX2-NEXT:    vse32.v v27, (a1)
+; LMULMAX2-NEXT:    ret
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craig.topper wrote:
> The elements we're looking for aren't guaranteed to be in v27. We only know the //minimum// width of a register is 128 bits. It might be 256 bits or more. In which case all 8 elements are all in v26. I think we have to always slide down to 0 using the full lmul.
Oh snap, you're right. Sliding down the full amount seems like the way to go.


Repository:
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  https://reviews.llvm.org/D97192/new/

https://reviews.llvm.org/D97192