[PATCH] D97111: [RISCV] change rvv frame layout

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:806-807
   const TargetRegisterClass *RC = &RISCV::GPRRegClass;
+
+  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
+  int64_t RVVStackSize = assignRVVStackObjectOffsets(MFI);
----------------



================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:831
+    return;
+  }
+  int64_t MinOffset = std::numeric_limits<int64_t>::max();
----------------



================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:837
+    if (MFI.getStackID(FrameIdx) != TargetStackID::Default)
+      continue;
+    int64_t Offset = MFI.getObjectOffset(FrameIdx);
----------------



================
Comment at: llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll:8
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    sub sp, sp, a0
-; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    add sp, sp, a0
+; CHECK-NEXT:    addi	sp, sp, -16
+; CHECK-NEXT:    csrr	a0, vlenb
----------------
What's up with all the whitespace changes? Those should have been normalised.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97111/new/

https://reviews.llvm.org/D97111