[PATCH] D88390: [M68k] (Patch 4/8) MC layer and object file support

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 accepted this revision.
jrtc27 added a comment.

A few minor remaining issues, but once those are fixed I believe this is fine to land.



================
Comment at: llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp:239
+                                         const MCTargetOptions &Options) {
+  // assert (TheTriple.getEnvironment() == Triple::GNU);
+  const Triple &TheTriple = STI.getTargetTriple();
----------------
Commented-out code


================
Comment at: llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp:216
+  for (uint64_t i = 0; i != NumNops; ++i) {
+    OS << "\x4E\x71";
+  }
----------------
rengolin wrote:
> Isn't there a better way to emit this?
This is how RISC-V does it (well, with `OS.write("\x13\0\0\0", 4);` and a similar one for 2-byte compressed instructions), so this is fine?


================
Comment at: llvm/lib/Target/M68k/MCTargetDesc/M68kELFObjectWriter.cpp:63
+
+// FIXME Handle reloc differences between pre-M68020 models and successors
+unsigned M68kELFObjectWriter::getRelocType(MCContext &Ctx,
----------------
jrtc27 wrote:
> This is odd; processors shouldn't care about fixups. But regardless of the actual problem, more info would be helpful as this isn't particularly useful for anyone who doesn't already know the problem.
Please clarify this comment or delete if it it's wrong


================
Comment at: llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp:378-381
+    // Since M68k is Big Endian we need to rotate each instruction word
+    while (Offset / 16) {
+      OS.write((char)((Buffer >> 8) & 0xFF));
+      OS.write((char)((Buffer >> 0) & 0xFF));
----------------
should work as a nicer way to write that (using llvm/Support/EndianStream.h)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88390/new/

https://reviews.llvm.org/D88390