[PATCH] D97194: [RISCV] Support fixed-length vector sign/zero extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll:15
+; CHECK-NEXT:    vle8.v v25, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsext.vf4 v28, v25
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This is using LMUL 4 for a result that fits in 128 bits. Should we be getting the container from the destination and deriving the source lmul from it instead?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97194/new/

https://reviews.llvm.org/D97194