[PATCH] D97097: [RISCV] Custom isel the rest of the vector load/store intrinsics.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

LGTM.



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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:67
 
 static RISCVVLMUL getLMUL(MVT VT) {
+  unsigned KnownSize = VT.getSizeInBits().getKnownMinValue();
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This'll need a rebase as it's now in `RISCVISelLowering`. But this will allow me to get rid of `getRegClassIDForVecVT`, so thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97097/new/

https://reviews.llvm.org/D97097