[PATCH] D96469: [AMDGPU] WIP: use single cache policy operand

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D96469#2574029 <https://reviews.llvm.org/D96469#2574029>, @foad wrote:

> In D96469#2573222 <https://reviews.llvm.org/D96469#2573222>, @rampitec wrote:
>
>> Rebased to support SCC.
>> I had to use bit 5 in CPol because bit 4 is used by SWZ in some buffer intrinsics which is already a public interface. Not sure why SWZ was combined with cache policy.
>
> See @piotr's comment in https://reviews.llvm.org/D68200#1688133.

I can w/a swz by masking the bit like here, but it still  doesn't belong to cache policy. We could argue that we can instead combine all optional operand bits into a single uint64_t which might make sense as it will allow free ordering in the asm, but that will lead to a huge custom code in asm parser too. Setting aside asm parsing problem from MIR representation I still think a single operand for a cache policy, and another for buf properties, and another for mimg properties is better, but I think that ship has sailed.


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