[PATCH] D96469: [AMDGPU] WIP: use single cache policy operand

Fri Feb 19 00:51:59 PST 2021

foad added a subscriber: piotr.
foad added a comment.

In D96469#2573222 <https://reviews.llvm.org/D96469#2573222>, @rampitec wrote:

> Rebased to support SCC.
> I had to use bit 5 in CPol because bit 4 is used by SWZ in some buffer intrinsics which is already a public interface. Not sure why SWZ was combined with cache policy.

See @piotr's comment in https://reviews.llvm.org/D68200#1688133.

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