[PATCH] D97124: [KnownBits][RISCV] Improve known bits for srem.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 325259.
craig.topper added a comment.

Improve the comment about why this is valid.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97124/new/

https://reviews.llvm.org/D97124

Files:
  llvm/lib/Support/KnownBits.cpp
  llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll


Index: llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
+++ llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
@@ -1114,8 +1114,6 @@
 ; RV64IM-LABEL: sext_i32_remw_zext_sext_i16:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    rem a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %3 = sext i16 %1 to i32
   %4 = zext i16 %0 to i32
Index: llvm/lib/Support/KnownBits.cpp
===================================================================
--- llvm/lib/Support/KnownBits.cpp
+++ llvm/lib/Support/KnownBits.cpp
@@ -473,10 +473,11 @@
     return Known;
   }
 
-  // The sign bit is the LHS's sign bit, except when the result of the
-  // remainder is zero. If it's known zero, our sign bit is also zero.
-  if (LHS.isNonNegative())
-    Known.makeNonNegative();
+  // The result has the same sign as the left hand side and the magnitude of
+  // the result is less than or equal to the magnitude of the left hand side.
+  // Any leading zeros that exist in the left hand side must also exist in
+  // the result.
+  Known.Zero.setHighBits(LHS.countMinLeadingZeros());
   return Known;
 }
 


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