[PATCH] D97124: [KnownBits][RISCV] Improve known bits for srem.

[Craig Topper via Phabricator via llvm-commits]

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The result must be less than or equal to the LHS side, so any
leading zeros in the left hand side must also exist in the result.
This is stronger than the previous behavior where we only considered
the sign bit being 0.

The affected test case used the sign bit being known 0 to change
a sign extend to a zero extend pre type legalization. After type
legalization the types were promoted to i64, but we no longer
knew bit 31 was zero. This shifts are are the equivalent of an
AND with 0xffffffff or zext_inreg X, i32. This patch allows us to
see that bit 31 is zero and remove the shifts.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97124

Files:
  llvm/lib/Support/KnownBits.cpp
  llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll


Index: llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
+++ llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
@@ -1114,8 +1114,6 @@
 ; RV64IM-LABEL: sext_i32_remw_zext_sext_i16:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    rem a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %3 = sext i16 %1 to i32
   %4 = zext i16 %0 to i32
Index: llvm/lib/Support/KnownBits.cpp
===================================================================
--- llvm/lib/Support/KnownBits.cpp
+++ llvm/lib/Support/KnownBits.cpp
@@ -473,10 +473,9 @@
     return Known;
   }
 
-  // The sign bit is the LHS's sign bit, except when the result of the
-  // remainder is zero. If it's known zero, our sign bit is also zero.
-  if (LHS.isNonNegative())
-    Known.makeNonNegative();
+  // The result is less than or equal to the left hand side. Any leading
+  // zero bits in the LHS must also exist in the result.
+  Known.Zero.setHighBits(LHS.countMinLeadingZeros());
   return Known;
 }
 


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