[PATCH] D97033: [RISCV] Use custom isel for vector indexed load/store intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D97033#2574061 <https://reviews.llvm.org/D97033#2574061>, @craig.topper wrote:

> In D97033#2574046 <https://reviews.llvm.org/D97033#2574046>, @frasercrmck wrote:
>
>> I'm wondering if this has any implications on the masked scatter/gather intrinsics. I had previously copied this TableGen, knowing that we only use a small subset of the valid permutation of VTs for scatter/gather. I was going to look at that later. However, with this change I can see that an alternative lowering scheme would be to lower them to the intrinsics. Any thoughts about that?
>
> That’s a good idea. I’ve been thinking about the same thing for the other ISD opcodes we’ve added. But I haven’t come to any conclusions. Having 3 different ways of selecting the same instruction seems wasteful for the isel table. The isel table isn’t very efficient either for the number of types we have.

If we go the route of reusing these intrinsics for gather/scatter we should probably fix them to carry a memory operand into machine IR properly so we don't drop the one from the gather/scatter node.


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