[PATCH] D97055: [RISCV] Improve register allocation around vector masks

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck updated this revision to Diff 324993.
frasercrmck added a comment.

- update test run line


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97055/new/

https://reviews.llvm.org/D97055

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir


Index: llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
@@ -0,0 +1,34 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+# RUN:     -start-after finalize-isel -stop-after prologepilog -o - %s | FileCheck %s
+
+--- |
+  define void @mask_reg_alloc() {
+    ret void
+  }
+...
+---
+name: mask_reg_alloc
+tracksRegLiveness: true
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $v0, $v1, $v2, $v3
+    ; CHECK-LABEL: name: mask_reg_alloc
+    ; CHECK: liveins: $v0, $v1, $v2, $v3
+    ; CHECK: renamable $v25 = PseudoVMERGE_VIM_M1 killed renamable $v2, 1, killed renamable $v0, $noreg, -1, implicit $vl, implicit $vtype
+    ; CHECK: renamable $v0 = COPY killed renamable $v1
+    ; CHECK: renamable $v26 = PseudoVMERGE_VIM_M1 killed renamable $v3, 1, killed renamable $v0, $noreg, -1, implicit $vl, implicit $vtype
+    ; CHECK: renamable $v0 = PseudoVADD_VV_M1 killed renamable $v25, killed renamable $v26, $noreg, -1, implicit $vl, implicit $vtype
+    ; CHECK: PseudoRET implicit $v0
+    %0:vr = COPY $v0
+    %1:vr = COPY $v1
+    %2:vr = COPY $v2
+    %3:vr = COPY $v3
+    %4:vmv0 = COPY %0
+    %5:vrnov0 = PseudoVMERGE_VIM_M1 killed %2, 1, %4, $noreg, -1, implicit $vl, implicit $vtype
+    %6:vmv0 = COPY %1
+    %7:vrnov0 = PseudoVMERGE_VIM_M1 killed %3, 1, %6, $noreg, -1, implicit $vl, implicit $vtype
+    %8:vr = PseudoVADD_VV_M1 killed %5, killed %7, $noreg, -1, implicit $vl, implicit $vtype
+    $v0 = COPY %8
+    PseudoRET implicit $v0
+...
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -59,6 +59,10 @@
                      unsigned Kind = 0) const override {
     return &RISCV::GPRRegClass;
   }
+
+  const TargetRegisterClass *
+  getLargestLegalSuperClass(const TargetRegisterClass *RC,
+                            const MachineFunction &) const override;
 };
 }
 
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -296,3 +296,11 @@
     return CSR_ILP32D_LP64D_RegMask;
   }
 }
+
+const TargetRegisterClass *
+RISCVRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
+                                             const MachineFunction &) const {
+  if (RC == &RISCV::VMV0RegClass)
+    return &RISCV::VRRegClass;
+  return RC;
+}


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D97055.324993.patch
Type: text/x-patch
Size: 2755 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210219/3391307d/attachment.bin>