[PATCH] D97055: [RISCV] Improve register allocation around vector masks

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

This has been on my list for a while since @rogfer01 brought it up after D94294 <https://reviews.llvm.org/D94294>. I just encountered it myself so thought I'd nip it in the bud.

I'll include the diff on the test here. I can precommit it if people think it's adequate.

  --- a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
  +++ b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
  @@ -15,24 +15,10 @@ body:             |
       liveins: $v0, $v1, $v2, $v3
       ; CHECK-LABEL: name: mask_reg_alloc
       ; CHECK: liveins: $v0, $v1, $v2, $v3
  -    ; CHECK: CFI_INSTRUCTION def_cfa_offset 0
  -    ; CHECK: $x10 = PseudoReadVLENB
  -    ; CHECK: $x10 = SLLI killed $x10, 1
  -    ; CHECK: $x2 = SUB $x2, killed $x10
  -    ; CHECK: PseudoVSPILL_M1 $v0, $x2 :: (store unknown-size into %stack.1, align 8)
  -    ; CHECK: $x10 = PseudoReadVLENB
  -    ; CHECK: $x10 = ADD $x2, killed $x10
  -    ; CHECK: PseudoVSPILL_M1 $v1, killed $x10 :: (store unknown-size into %stack.0, align 8)
  -    ; CHECK: renamable $v0 = PseudoVRELOAD_M1 $x2 :: (load unknown-size from %stack.1, align 8)
       ; CHECK: renamable $v25 = PseudoVMERGE_VIM_M1 killed renamable $v2, 1, killed renamable $v0, $noreg, -1, implicit $vl, implicit $vtype
  -    ; CHECK: $x10 = PseudoReadVLENB
  -    ; CHECK: $x10 = ADD $x2, killed $x10
  -    ; CHECK: renamable $v0 = PseudoVRELOAD_M1 killed $x10 :: (load unknown-size from %stack.0, align 8)
  +    ; CHECK: renamable $v0 = COPY killed renamable $v1
       ; CHECK: renamable $v26 = PseudoVMERGE_VIM_M1 killed renamable $v3, 1, killed renamable $v0, $noreg, -1, implicit $vl, implicit $vtype
       ; CHECK: renamable $v0 = PseudoVADD_VV_M1 killed renamable $v25, killed renamable $v26, $noreg, -1, implicit $vl, implicit $vtype
  -    ; CHECK: $x10 = PseudoReadVLENB
  -    ; CHECK: $x10 = SLLI killed $x10, 1
  -    ; CHECK: $x2 = ADD $x2, killed $x10
       ; CHECK: PseudoRET implicit $v0
       %0:vr = COPY $v0
       %1:vr = COPY $v1


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97055/new/

https://reviews.llvm.org/D97055