[PATCH] D96980: [amdgpu] Revert agnostic SGPR spill.

[Michael Liao via Phabricator via llvm-commits]

hliao added a comment.

In D96980#2574001 <https://reviews.llvm.org/D96980#2574001>, @critson wrote:

> Is it at all possible to encapsulate your failure case in a lit test?
>
> Is the problem not with the exec manipulation, but really that the register scavenger choosing an inappropriate register, w.r.t. wave level CFG?

The register scavenge may be improved to a better candidate without live values in the inactive lanes. But, we should the cases where such a candidate is not available at all. The issue is exactly from the explicit exec mask manipulation, which doesn't honor the current exec mask and tries to access the inactive parts. Without inactive lanes being protected, we would always have the issue.


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