[PATCH] D97035: [AArch64][GlobalISel] Support lowering <1 x i8> arguments and returning

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/CodeGen/GlobalISel/CallLowering.cpp:551
+          LLVM_DEBUG(dbgs() << "Incoming promoted vector arg elts is not a "
+                               "multiple of orig type elt");
           return false;
----------------
Missing newline


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Comment at: llvm/lib/CodeGen/GlobalISel/CallLowering.cpp:559-560
+          DstTys.push_back(OrigTy);
+        auto Unmerge = MIRBuilder.buildUnmerge(DstTys, {NewReg});
         MIRBuilder.buildCopy(ArgReg, Unmerge.getReg(0));
       } else {
----------------
Can't you directly unmerge into ArgReg?


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Comment at: llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp:389
+                Srcs.push_back(Undef.getReg(0));
+              CurVReg = MIRBuilder.buildBuildVector({NewLLT}, Srcs).getReg(0);
             }
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I am working on the return complement to 62d946e133f748d4500903c2b80fc456ff409505 which will handle more cases here


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97035/new/

https://reviews.llvm.org/D97035