[PATCH] D97033: [RISCV] Use custom isel for vector indexed load/store intrinsics.

Fraser Cormack via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Feb 19 01:02:33 PST 2021


frasercrmck added a comment.

I'm wondering if this has any implications on the masked scatter/gather intrinsics. I had previously copied this TableGen, knowing that we only use a small subset of the valid permutation of VTs for scatter/gather. I was going to look at that later. However, with this change I can see that an alternative lowering scheme would be to lower them to the intrinsics. Any thoughts about that?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97033/new/

https://reviews.llvm.org/D97033



More information about the llvm-commits mailing list