[llvm] 065a187 - [RISCV] Fix typo. Use ValueType instead of LLVMType.

Hsiangkai Wang via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 18 07:22:02 PST 2021


Author: Hsiangkai Wang
Date: 2021-02-18T23:21:27+08:00
New Revision: 065a187f337f2a3204c69c2a73a65aad49a44be1

URL: https://github.com/llvm/llvm-project/commit/065a187f337f2a3204c69c2a73a65aad49a44be1
DIFF: https://github.com/llvm/llvm-project/commit/065a187f337f2a3204c69c2a73a65aad49a44be1.diff

LOG: [RISCV] Fix typo. Use ValueType instead of LLVMType.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index a98bb0f13c49..ea0e5f137359 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -65,7 +65,7 @@ multiclass VPatUSLoadStoreSDNode<ValueType type,
             (store_instr reg_class:$rs2, BaseAddr:$rs1, avl, sew)>;
 }
 
-multiclass VPatUSLoadStoreWholeVRSDNode<LLVMType type,
+multiclass VPatUSLoadStoreWholeVRSDNode<ValueType type,
                                         int sew,
                                         LMULInfo vlmul,
                                         VReg reg_class>


        


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