[llvm] e6064a6 - [GlobalISel] Implement computeKnownBits for G_ASSERT_SEXT

[Jessica Paquette via llvm-commits]

Author: Jessica Paquette
Date: 2021-02-17T14:00:36-08:00
New Revision: e6064a6418f31d7140de97a99e9df25aeef66811

URL: https://github.com/llvm/llvm-project/commit/e6064a6418f31d7140de97a99e9df25aeef66811
DIFF: https://github.com/llvm/llvm-project/commit/e6064a6418f31d7140de97a99e9df25aeef66811.diff

LOG: [GlobalISel] Implement computeKnownBits for G_ASSERT_SEXT

Implementation is the same as G_SEXT_INREG.

Differential Revision: https://reviews.llvm.org/D96899

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
    llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
index 3d8b29814198..97aa094cfbc5 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
@@ -347,6 +347,7 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
     Known = Known.sext(BitWidth);
     break;
   }
+  case TargetOpcode::G_ASSERT_SEXT:
   case TargetOpcode::G_SEXT_INREG: {
     computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
                          Depth + 1);

diff  --git a/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp b/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
index 5b365a5e3a1f..eacad3469e5e 100644
--- a/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
@@ -842,6 +842,77 @@ TEST_F(AArch64GISelMITest, TestKnownBitsSextInReg) {
   EXPECT_EQ(1u, Res.Zero.getZExtValue());
 }
 
+TEST_F(AArch64GISelMITest, TestKnownBitsAssertSext) {
+  StringRef MIRString = R"(
+   ; 000...0001
+   %one:_(s32) = G_CONSTANT i32 1
+
+   ; 000...0010
+   %two:_(s32) = G_CONSTANT i32 2
+
+   ; 000...1010
+   %ten:_(s32) = G_CONSTANT i32 10
+
+   ; ???...????
+   %w0:_(s32) = COPY $w0
+
+   ; ???...?1?
+   %or:_(s32) = G_OR %w0, %two
+
+   ; All bits are known.
+   %assert_sext1:_(s32) = G_ASSERT_SEXT %one, 1
+   %copy_assert_sext1:_(s32) = COPY %assert_sext1
+
+   ; All bits unknown
+   %assert_sext2:_(s32) = G_ASSERT_SEXT %or, 1
+   %copy_assert_sext2:_(s32) = COPY %assert_sext2
+
+   ; Extending from the only (known) set bit
+   ; 111...11?
+   %assert_sext3:_(s32) = G_ASSERT_SEXT %or, 2
+   %copy_assert_sext3:_(s32) = COPY %assert_sext3
+
+   ; Extending from a known set bit, overwriting all of the high set bits.
+   ; 111...1110
+   %assert_sext4:_(s32) = G_ASSERT_SEXT %ten, 2
+   %copy_assert_sext4:_(s32) = COPY %assert_sext4
+)";
+  setUp(MIRString);
+  if (!TM)
+    return;
+  GISelKnownBits Info(*MF);
+  KnownBits Res;
+  auto GetKB = [&](unsigned Idx) {
+    Register CopyReg = Copies[Idx];
+    auto *Copy = MRI->getVRegDef(CopyReg);
+    return Info.getKnownBits(Copy->getOperand(1).getReg());
+  };
+
+  // Every bit is known to be a 1.
+  Res = GetKB(Copies.size() - 4);
+  EXPECT_EQ(32u, Res.getBitWidth());
+  EXPECT_TRUE(Res.isAllOnes());
+
+  // All bits are unknown
+  Res = GetKB(Copies.size() - 3);
+  EXPECT_EQ(32u, Res.getBitWidth());
+  EXPECT_TRUE(Res.isUnknown());
+
+  // Extending from the only known set bit
+  // 111...11?
+  Res = GetKB(Copies.size() - 2);
+  EXPECT_EQ(32u, Res.getBitWidth());
+  EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
+  EXPECT_EQ(0u, Res.Zero.getZExtValue());
+
+  // Extending from a known set bit, overwriting all of the high set bits.
+  // 111...1110
+  Res = GetKB(Copies.size() - 1);
+  EXPECT_EQ(32u, Res.getBitWidth());
+  EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
+  EXPECT_EQ(1u, Res.Zero.getZExtValue());
+}
+
 TEST_F(AArch64GISelMITest, TestKnownBitsMergeValues) {
   StringRef MIRString = R"(
    %val0:_(s16) = G_CONSTANT i16 35224