[PATCH] D96469: [AMDGPU] WIP: use single cache policy operand

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:4904
+  // since parseOptionalOperand just consumed all of the individual bits.
+  if (ResTy == MatchOperand_Success &&
+      (Mnemonic.startswith("scratch_") || Mnemonic.startswith("flat_") ||
----------------
dp wrote:
> Should also combine cache policy operands on MatchOperand_NoMatch condition, otherwise these operands may break operand matcher later and may result in an invalid error position. For example:
> 
>     error: invalid operand for instruction
>     global_atomic_add v0, v[1:2], v2, off glc 1
>                                           ^
> 
> Hopefully the whole hack will be removed in final version.
OK. Although it shall really migrate into parseOptionalOperand() when all instruction classes are covered.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96469/new/

https://reviews.llvm.org/D96469