[PATCH] D96732: AMDGPU: Use kill instruction to hint soft clause live ranges

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, tpr, foad, vpykhtin, kerbowa, cfang.
Herald added subscribers: jfb, mgrang, hiraditya, t-tye, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, qcolombet.
arsenm requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

Previously we would use a bundle to hint the register allocator to not
overwrite the pointers in a sequence of loads to avoid breaking soft
clauses. This bundling was based on a fuzzy register pressure
heuristic, so we could not guarantee using more registers than are
really available. This would result in register allocator failing on
unsatisfiable bundles. Use a kill to artificially extend the live
ranges, so we can always succeed at register allocation even if it
means extra spills in the worst case.

      

This seems to capture most of the benefit of the bundle while avoiding
most of the risk presented by the bundle. However the lit tests do
show a handful of regressions. In some cases with sequences of
volatile loads, unused load components end up getting reallocated to
the next load which forces a wait between. There are also a few small
scheduling regressions where a hazard used to be avoided, and one
spill torture test which for some reason nearly doubles the stack
usage. There is also a bit of noise from leftover kills (it may make
sense for post-RA pseudos to strip all of these out).


https://reviews.llvm.org/D96732

Files:
  llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
  llvm/test/CodeGen/AMDGPU/disable_form_clauses.ll
  llvm/test/CodeGen/AMDGPU/ds_write2.ll
  llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
  llvm/test/CodeGen/AMDGPU/idot2.ll
  llvm/test/CodeGen/AMDGPU/idot4s.ll
  llvm/test/CodeGen/AMDGPU/idot4u.ll
  llvm/test/CodeGen/AMDGPU/idot8s.ll
  llvm/test/CodeGen/AMDGPU/idot8u.ll
  llvm/test/CodeGen/AMDGPU/limit-soft-clause-reg-pressure.mir
  llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
  llvm/test/CodeGen/AMDGPU/memory_clause.ll
  llvm/test/CodeGen/AMDGPU/memory_clause.mir
  llvm/test/CodeGen/AMDGPU/soft-clause-dbg-value.mir
  llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
  llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
  llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
  llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll