[PATCH] D96567: [RISCV] Add support for fixed vector floating point setcc.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:84
+                            SDTypeProfile<1, 5, [SDTCisVec<0>,
+                                                 SDTCVecEltisVT<0, i1>,
+                                                 SDTCisVec<1>,
----------------
frasercrmck wrote:
> I was wondering if this warrants a `SDTCisVecWithSameNumEltsAndEltVT<opidx, otheropidx, eltvt>` to combine these three commonly-used constraints (`SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>, SDTCVecEltisVT<0, X>`) but the name alone gives me second thoughts.
I think the tablegen backend maps the name of the class to dispatch to a function that does the type constraining. 

I suspect SDTCisVec is redundant if SDTCVecEltisVT is specified.


Repository:
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  https://reviews.llvm.org/D96567/new/

https://reviews.llvm.org/D96567