[PATCH] D96336: [AMDGPU] Save VGPR of whole wave when spilling

[Sebastian Neubauer via Phabricator via llvm-commits]

sebastian-ne added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:117-118
+// be live in a currently inactive lane, but LLVM does not track this.
+def FAKE_DEF : PseudoInstSI <(outs unknown:$vdst), (ins),
+  [], ";;#FAKE_DEF $vdst">;
+
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arsenm wrote:
> I think a better name would be something like COPY_INACTIVE_LANES or something like that?
Hm, it doesn’t really copy anything. (Also, the VGPR could be dead in other lanes as well.) How about DEF_INACTIVE_LANES?


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1029
+/// then flip EXEC (EXEC = EXEC ^ -1), then save the rest of the lanes and flip
+/// EXEC again to restore its original value.
+void SIRegisterInfo::buildWaveVGPRSpillLoadStore(MachineBasicBlock::iterator MI,
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arsenm wrote:
> Can you spell out the expected instruction sequence in the comment
I added a comment with generated instructions  in D96517 (SIRegisterInfo.cpp:L1449).

Direct link (will cease to work when the review is updated): https://reviews.llvm.org/D96517#C2404245NL1449


Repository:
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  https://reviews.llvm.org/D96336/new/

https://reviews.llvm.org/D96336