[PATCH] D96469: [AMDGPU] WIP: use single cache policy operand

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
rampitec added reviewers: dp, arsenm.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
rampitec requested review of this revision.
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This is WIP and incomplete. A pilot change to discuss if we want this or not.

I am proposing to replace individual operands GLC, SLC, and DLC with a single
cache_policy bitmask operand. This will reduce the number of operands in MIR
and I hope the amount of code. These operands are mostly 0 anyway.

Additional advantage that parser will accept these flags in any order unlike
now.

Selection is not done yet and only scratch instructions covered. It passes
check-llvm-mc though (but does not pass codegen tests of course).


https://reviews.llvm.org/D96469

Files:
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/lib/Target/AMDGPU/FLATInstructions.td
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
  llvm/lib/Target/AMDGPU/SIDefines.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.td

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