[PATCH] D96423: [DebugInfo] Remove early implicit cast of TypeSize to unsigned
Joe Ellis via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 11 02:03:19 PST 2021
joechrisellis updated this revision to Diff 322925.
joechrisellis marked an inline comment as done.
joechrisellis added a comment.
Address @david-arm's comments.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D96423/new/
https://reviews.llvm.org/D96423
Files:
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -1321,10 +1321,11 @@
if (auto Fragment = Expr->getFragmentInfo())
BitsToDescribe = Fragment->SizeInBits;
for (auto RegAndSize : RFV.getRegsAndSizes()) {
- unsigned RegisterSize = RegAndSize.second;
// Bail out if all bits are described already.
if (Offset >= BitsToDescribe)
break;
+ // TODO: handle scalable vectors.
+ unsigned RegisterSize = RegAndSize.second;
unsigned FragmentSize = (Offset + RegisterSize > BitsToDescribe)
? BitsToDescribe - Offset
: RegisterSize;
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