[PATCH] D96423: [DebugInfo] Remove early implicit cast of TypeSize to unsigned
David Sherwood via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 11 01:51:33 PST 2021
david-arm added inline comments.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:1324
for (auto RegAndSize : RFV.getRegsAndSizes()) {
- unsigned RegisterSize = RegAndSize.second;
// Bail out if all bits are described already.
----------------
I'm not sure this is the right thing to do here. I realise you want a quick workaround, but I think the better workaround for now is to simply move this down until after the bail out below and add a TODO that this needs updating for scalable vectors perhaps?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D96423/new/
https://reviews.llvm.org/D96423
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