[PATCH] D96423: [DebugInfo] Remove early implicit cast of TypeSize to unsigned

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:1324
         for (auto RegAndSize : RFV.getRegsAndSizes()) {
-          unsigned RegisterSize = RegAndSize.second;
           // Bail out if all bits are described already.
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I'm not sure this is the right thing to do here. I realise you want a quick workaround, but I think the better workaround for now is to simply move this down until after the bail out below and add a TODO that this needs updating for scalable vectors perhaps?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96423/new/

https://reviews.llvm.org/D96423