[PATCH] D96352: [RISCV] Initial support for insert/extract subvector

[ShihPo Hung via Phabricator via llvm-commits]

arcbbb added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:38
+
+  unsigned LMul = Subtarget->getLMULForFixedLengthVector(VT);
+  unsigned RCID;
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craig.topper wrote:
> arcbbb wrote:
> > craig.topper wrote:
> > > Would it be simpler to get the LMUL from the size of the fixed part of the scalable type? We don't need subtarget for that.
> > I was considering it was possible to insert/extract an M1 fixed-width vector into/from an M2 scalable vector, so I get the LMUL from the fixed-width one.
> If that happened. I think we would need to create an EXTRACT_SUBREG/INSERT_SUBREG for the register allocator to make sense of it.
Got it! I changed it to `getRegClassIDForLMUL`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96352/new/

https://reviews.llvm.org/D96352