[PATCH] D96336: [AMDGPU] Save VGPR of whole wave when spilling

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1433
+    // lanes of the chosen VGPR. Pick v0 because it doesn't make a difference.
+    Register TmpVGPR = AMDGPU::VGPR0;
     RS->setRegUsed(TmpVGPR);
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If the scavenger finds a vgpr that it thinks is dead, would that mean we only have to save the inactive lanes?


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Comment at: llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll:49
 ; GFX6: s_add_u32 s32, s32, 0x[[OFFSET:[0-9a-f]+]]
+; GFX6-NEXT: s_waitcnt expcnt(0)
 ; GFX6-NEXT: buffer_load_dword v{{[0-9]+}}, off, s[{{[0-9:]+}}], s32
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What causes this change?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96336/new/

https://reviews.llvm.org/D96336