[PATCH] D96336: [AMDGPU] Save VGPR of whole wave when spilling

[Sebastian Neubauer via Phabricator via llvm-commits]

sebastian-ne created this revision.
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Spilling SGPRs to scratch uses a temporary VGPR. LLVM currently cannot
determine if a VGPR is used in other lanes or not, so we need to save
all lanes of the VGPR.
As no SGPR is available either, we save currently active lanes of the
temporary VGPR, then flip all bits in EXEC, then save the previously
inactive lanes, then restore EXEC by flipping all bits again.

We need to save the VGPR even if it is marked as dead. The MIR verifier
complains when saving a dead register, so we mark it as live with inline
assembly. Another inline assembly block is used to create a use of the
restored VGPR. (Is this necessary? I.e. can LLVM remove a load in MIR if
the result is never used?)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96336

Files:
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
  llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
  llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
  llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
  llvm/test/CodeGen/AMDGPU/spill-m0.ll
  llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll

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