[PATCH] D95086: [DAGCombiner] Transform (zext (select c, load1, load2)) -> (select c, zextload1, zextload2)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:10017
+      !TLI.isLoadExtLegal(ExtLoadOpcode, VT, Load2->getMemoryVT()))
+    return SDValue();
+
----------------
I'm not sure if this correctly handles the case where Opcode is ANY_EXTEND and the existing loads are SEXT/ZEXT - in which case we need to ensure the final (legal) loads are fully SEXT/ZEXT loads - even though we don't care about the new extended bits we do still need the 'middle' extended bits to be correct.

Does that make sense? I'm not certain if this is handled - I may have gotten this wrong and haven't gotten a test case for this.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95086/new/

https://reviews.llvm.org/D95086