[PATCH] D95946: [AMDGPU] Save all lanes for reserved VGPRs

[Sebastian Neubauer via Phabricator via llvm-commits]

sebastian-ne added a comment.

This should only spill VGPRs that are used for SGPR→VGPR spills. These spills can overwrite VGPRs from inactive lanes. Other caller-save registers should not be saved by the callee.
For whole wave mode, I still need to write a patch. It should work similar like here.

In the end, new saves are inserted for SGPR→VGPR spills if the VGPR is caller-save (callee-save VGPRs are already saved)
and WWM reserved registers.

Clobbered caller-save registers that are neither used for SGPR spills nor WWM are not saved in the callee.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D95946/new/

https://reviews.llvm.org/D95946