[PATCH] D95946: [AMDGPU] Save all lanes for reserved VGPRs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Can we avoid spilling the clobbered registers if we know the function doesn't use whole wave mode?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D95946/new/

https://reviews.llvm.org/D95946