[PATCH] D95866: [X86][SSE] Support variable-index float/double vector insertion on SSE41+ targets (PR47924)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In D95866#2538096 <https://reviews.llvm.org/D95866#2538096>, @pengfei wrote:

> One more question: if the simd registers are in high pressure, can we get the benefit as expected?

I'm going to say "probably" :) The big benefit is that we avoid the scalar write aliasing with a vector write, which can stall various cache optimizations (STLF etc.) - instead we're likely to end up with a single vector push/pull which should be a lot less painful. However, the (V)BLENDVPD/S op isn't commutable so if we end up spilling the wrong vector (or in the SSE case the xmm0 tied register causes problems) then we could see additional stack traffic - I don't think that is a showstopper however, and is something I think we could address in regalloc if it does happen.


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