[PATCH] D95866: [X86][SSE] Support variable-index float/double vector insertion on SSE41+ targets (PR47924)

[Pengfei Wang via Phabricator via llvm-commits]

pengfei added a comment.

One more question: if the simd registers are in high pressure, can we get the benefit as expected?


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  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D95866/new/

https://reviews.llvm.org/D95866