[PATCH] D95890: [RISCV] Alternate attempt to optimize sign-extended EXTRACT_VECTOR_ELT nodes.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

Cheers. I'm happy for you to split the DAGCombiner bits off into a separate patch. I can update mine as required.



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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:8371
                          N0.getOperand(0), DAG.getValueType(ExtVT));
+    // Even if we can't convert to sext_inreg, we might be able to remove
+    // this shift pair if the input is already sign extended.
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Ah, excellent: so this is what I was missing. I'm surprised this wasn't already there.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95890/new/

https://reviews.llvm.org/D95890