[PATCH] D95800: [RISCV] Make scalable vector FMA commutable for register allocation.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1105
+  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
+}
+#undef CASE_VFMA_CHANGE_OPCODE_SPLATS
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I'd leave a blank line after this given there's one between the macro definitions and the function


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95800/new/

https://reviews.llvm.org/D95800