[PATCH] D95800: [RISCV] Make scalable vector FMA commutable for register allocation.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:899
+  CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF8)                                       \
+      : case CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4)                            \
+      : case CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2)                            \
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Ouch; maybe tactful use of `// clang-format [on|off]` around these macro definitions would be better?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95800/new/

https://reviews.llvm.org/D95800