[llvm] b4106f9 - [RISCV] Fix incorrect RVV sdiv/udiv lowering
Fraser Cormack via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 2 10:42:39 PST 2021
Author: Fraser Cormack
Date: 2021-02-02T18:35:53Z
New Revision: b4106f9c7b8c498d109301ced7bf9aca32027168
URL: https://github.com/llvm/llvm-project/commit/b4106f9c7b8c498d109301ced7bf9aca32027168
DIFF: https://github.com/llvm/llvm-project/commit/b4106f9c7b8c498d109301ced7bf9aca32027168.diff
LOG: [RISCV] Fix incorrect RVV sdiv/udiv lowering
Due to a clerical error, the sdiv operation was mapping to vdivu and
udiv to vdiv, when the opposite mapping is the correct one.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D95869
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 0ffa022d64d8..24f2c3510128 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -438,8 +438,8 @@ defm "" : VPatBinarySDNode_VV_VX<mulhs, "PseudoVMULH">;
defm "" : VPatBinarySDNode_VV_VX<mulhu, "PseudoVMULHU">;
// 12.11. Vector Integer Divide Instructions
-defm "" : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIVU">;
-defm "" : VPatBinarySDNode_VV_VX<udiv, "PseudoVDIV">;
+defm "" : VPatBinarySDNode_VV_VX<udiv, "PseudoVDIVU">;
+defm "" : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIV">;
defm "" : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU">;
defm "" : VPatBinarySDNode_VV_VX<srem, "PseudoVREM">;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
index 239151274c4e..bbfc09d1c276 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
@@ -5,7 +5,7 @@ define <vscale x 1 x i8> @vdiv_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8
; CHECK-LABEL: vdiv_vv_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 1 x i8> %va, %vb
ret <vscale x 1 x i8> %vc
@@ -15,7 +15,7 @@ define <vscale x 1 x i8> @vdiv_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vdiv_vx_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -70,7 +70,7 @@ define <vscale x 2 x i8> @vdiv_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8
; CHECK-LABEL: vdiv_vv_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 2 x i8> %va, %vb
ret <vscale x 2 x i8> %vc
@@ -80,7 +80,7 @@ define <vscale x 2 x i8> @vdiv_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vdiv_vx_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -111,7 +111,7 @@ define <vscale x 4 x i8> @vdiv_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8
; CHECK-LABEL: vdiv_vv_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 4 x i8> %va, %vb
ret <vscale x 4 x i8> %vc
@@ -121,7 +121,7 @@ define <vscale x 4 x i8> @vdiv_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vdiv_vx_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -152,7 +152,7 @@ define <vscale x 8 x i8> @vdiv_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8
; CHECK-LABEL: vdiv_vv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 8 x i8> %va, %vb
ret <vscale x 8 x i8> %vc
@@ -162,7 +162,7 @@ define <vscale x 8 x i8> @vdiv_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vdiv_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -193,7 +193,7 @@ define <vscale x 16 x i8> @vdiv_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16
; CHECK-LABEL: vdiv_vv_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v10
+; CHECK-NEXT: vdiv.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = sdiv <vscale x 16 x i8> %va, %vb
ret <vscale x 16 x i8> %vc
@@ -203,7 +203,7 @@ define <vscale x 16 x i8> @vdiv_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b
; CHECK-LABEL: vdiv_vx_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -234,7 +234,7 @@ define <vscale x 32 x i8> @vdiv_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32
; CHECK-LABEL: vdiv_vv_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v12
+; CHECK-NEXT: vdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = sdiv <vscale x 32 x i8> %va, %vb
ret <vscale x 32 x i8> %vc
@@ -244,7 +244,7 @@ define <vscale x 32 x i8> @vdiv_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b
; CHECK-LABEL: vdiv_vx_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -275,7 +275,7 @@ define <vscale x 64 x i8> @vdiv_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64
; CHECK-LABEL: vdiv_vv_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v16
+; CHECK-NEXT: vdiv.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = sdiv <vscale x 64 x i8> %va, %vb
ret <vscale x 64 x i8> %vc
@@ -285,7 +285,7 @@ define <vscale x 64 x i8> @vdiv_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b
; CHECK-LABEL: vdiv_vx_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
@@ -316,7 +316,7 @@ define <vscale x 1 x i16> @vdiv_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x
; CHECK-LABEL: vdiv_vv_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 1 x i16> %va, %vb
ret <vscale x 1 x i16> %vc
@@ -326,7 +326,7 @@ define <vscale x 1 x i16> @vdiv_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %
; CHECK-LABEL: vdiv_vx_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -357,7 +357,7 @@ define <vscale x 2 x i16> @vdiv_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x
; CHECK-LABEL: vdiv_vv_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 2 x i16> %va, %vb
ret <vscale x 2 x i16> %vc
@@ -367,7 +367,7 @@ define <vscale x 2 x i16> @vdiv_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %
; CHECK-LABEL: vdiv_vx_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -398,7 +398,7 @@ define <vscale x 4 x i16> @vdiv_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x
; CHECK-LABEL: vdiv_vv_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 4 x i16> %va, %vb
ret <vscale x 4 x i16> %vc
@@ -408,7 +408,7 @@ define <vscale x 4 x i16> @vdiv_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %
; CHECK-LABEL: vdiv_vx_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -439,7 +439,7 @@ define <vscale x 8 x i16> @vdiv_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x
; CHECK-LABEL: vdiv_vv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v10
+; CHECK-NEXT: vdiv.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = sdiv <vscale x 8 x i16> %va, %vb
ret <vscale x 8 x i16> %vc
@@ -449,7 +449,7 @@ define <vscale x 8 x i16> @vdiv_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %
; CHECK-LABEL: vdiv_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -480,7 +480,7 @@ define <vscale x 16 x i16> @vdiv_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x
; CHECK-LABEL: vdiv_vv_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v12
+; CHECK-NEXT: vdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = sdiv <vscale x 16 x i16> %va, %vb
ret <vscale x 16 x i16> %vc
@@ -490,7 +490,7 @@ define <vscale x 16 x i16> @vdiv_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signex
; CHECK-LABEL: vdiv_vx_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -521,7 +521,7 @@ define <vscale x 32 x i16> @vdiv_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x
; CHECK-LABEL: vdiv_vv_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v16
+; CHECK-NEXT: vdiv.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = sdiv <vscale x 32 x i16> %va, %vb
ret <vscale x 32 x i16> %vc
@@ -531,7 +531,7 @@ define <vscale x 32 x i16> @vdiv_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signex
; CHECK-LABEL: vdiv_vx_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
@@ -562,7 +562,7 @@ define <vscale x 1 x i32> @vdiv_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x
; CHECK-LABEL: vdiv_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 1 x i32> %va, %vb
ret <vscale x 1 x i32> %vc
@@ -572,7 +572,7 @@ define <vscale x 1 x i32> @vdiv_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
; CHECK-LABEL: vdiv_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -603,7 +603,7 @@ define <vscale x 2 x i32> @vdiv_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x
; CHECK-LABEL: vdiv_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 2 x i32> %va, %vb
ret <vscale x 2 x i32> %vc
@@ -613,7 +613,7 @@ define <vscale x 2 x i32> @vdiv_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
; CHECK-LABEL: vdiv_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -644,7 +644,7 @@ define <vscale x 4 x i32> @vdiv_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x
; CHECK-LABEL: vdiv_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v10
+; CHECK-NEXT: vdiv.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = sdiv <vscale x 4 x i32> %va, %vb
ret <vscale x 4 x i32> %vc
@@ -654,7 +654,7 @@ define <vscale x 4 x i32> @vdiv_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
; CHECK-LABEL: vdiv_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -685,7 +685,7 @@ define <vscale x 8 x i32> @vdiv_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x
; CHECK-LABEL: vdiv_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v12
+; CHECK-NEXT: vdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = sdiv <vscale x 8 x i32> %va, %vb
ret <vscale x 8 x i32> %vc
@@ -695,7 +695,7 @@ define <vscale x 8 x i32> @vdiv_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: vdiv_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -726,7 +726,7 @@ define <vscale x 16 x i32> @vdiv_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x
; CHECK-LABEL: vdiv_vv_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v16
+; CHECK-NEXT: vdiv.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = sdiv <vscale x 16 x i32> %va, %vb
ret <vscale x 16 x i32> %vc
@@ -736,7 +736,7 @@ define <vscale x 16 x i32> @vdiv_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
; CHECK-LABEL: vdiv_vx_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
@@ -767,7 +767,7 @@ define <vscale x 1 x i64> @vdiv_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x
; CHECK-LABEL: vdiv_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 1 x i64> %va, %vb
ret <vscale x 1 x i64> %vc
@@ -784,7 +784,7 @@ define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vsrl.vx v26, v26, a1
; CHECK-NEXT: vor.vv v25, v26, v25
-; CHECK-NEXT: vdivu.vv v8, v8, v25
+; CHECK-NEXT: vdiv.vv v8, v8, v25
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -825,7 +825,7 @@ define <vscale x 2 x i64> @vdiv_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x
; CHECK-LABEL: vdiv_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v10
+; CHECK-NEXT: vdiv.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = sdiv <vscale x 2 x i64> %va, %vb
ret <vscale x 2 x i64> %vc
@@ -842,7 +842,7 @@ define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vsrl.vx v28, v28, a1
; CHECK-NEXT: vor.vv v26, v28, v26
-; CHECK-NEXT: vdivu.vv v8, v8, v26
+; CHECK-NEXT: vdiv.vv v8, v8, v26
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -883,7 +883,7 @@ define <vscale x 4 x i64> @vdiv_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x
; CHECK-LABEL: vdiv_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v12
+; CHECK-NEXT: vdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = sdiv <vscale x 4 x i64> %va, %vb
ret <vscale x 4 x i64> %vc
@@ -900,7 +900,7 @@ define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: vsll.vx v12, v12, a1
; CHECK-NEXT: vsrl.vx v12, v12, a1
; CHECK-NEXT: vor.vv v28, v12, v28
-; CHECK-NEXT: vdivu.vv v8, v8, v28
+; CHECK-NEXT: vdiv.vv v8, v8, v28
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
@@ -941,7 +941,7 @@ define <vscale x 8 x i64> @vdiv_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x
; CHECK-LABEL: vdiv_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v16
+; CHECK-NEXT: vdiv.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = sdiv <vscale x 8 x i64> %va, %vb
ret <vscale x 8 x i64> %vc
@@ -958,7 +958,7 @@ define <vscale x 8 x i64> @vdiv_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; CHECK-NEXT: vsll.vx v24, v24, a1
; CHECK-NEXT: vsrl.vx v24, v24, a1
; CHECK-NEXT: vor.vv v16, v24, v16
-; CHECK-NEXT: vdivu.vv v8, v8, v16
+; CHECK-NEXT: vdiv.vv v8, v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
index 991cccf72cdd..b8f331e78b5b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
@@ -5,7 +5,7 @@ define <vscale x 1 x i8> @vdiv_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8
; CHECK-LABEL: vdiv_vv_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 1 x i8> %va, %vb
ret <vscale x 1 x i8> %vc
@@ -15,7 +15,7 @@ define <vscale x 1 x i8> @vdiv_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vdiv_vx_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -46,7 +46,7 @@ define <vscale x 2 x i8> @vdiv_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8
; CHECK-LABEL: vdiv_vv_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 2 x i8> %va, %vb
ret <vscale x 2 x i8> %vc
@@ -56,7 +56,7 @@ define <vscale x 2 x i8> @vdiv_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vdiv_vx_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -87,7 +87,7 @@ define <vscale x 4 x i8> @vdiv_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8
; CHECK-LABEL: vdiv_vv_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 4 x i8> %va, %vb
ret <vscale x 4 x i8> %vc
@@ -97,7 +97,7 @@ define <vscale x 4 x i8> @vdiv_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vdiv_vx_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -128,7 +128,7 @@ define <vscale x 8 x i8> @vdiv_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8
; CHECK-LABEL: vdiv_vv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 8 x i8> %va, %vb
ret <vscale x 8 x i8> %vc
@@ -138,7 +138,7 @@ define <vscale x 8 x i8> @vdiv_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
; CHECK-LABEL: vdiv_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -169,7 +169,7 @@ define <vscale x 16 x i8> @vdiv_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16
; CHECK-LABEL: vdiv_vv_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v10
+; CHECK-NEXT: vdiv.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = sdiv <vscale x 16 x i8> %va, %vb
ret <vscale x 16 x i8> %vc
@@ -179,7 +179,7 @@ define <vscale x 16 x i8> @vdiv_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b
; CHECK-LABEL: vdiv_vx_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -210,7 +210,7 @@ define <vscale x 32 x i8> @vdiv_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32
; CHECK-LABEL: vdiv_vv_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v12
+; CHECK-NEXT: vdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = sdiv <vscale x 32 x i8> %va, %vb
ret <vscale x 32 x i8> %vc
@@ -220,7 +220,7 @@ define <vscale x 32 x i8> @vdiv_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b
; CHECK-LABEL: vdiv_vx_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -251,7 +251,7 @@ define <vscale x 64 x i8> @vdiv_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64
; CHECK-LABEL: vdiv_vv_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v16
+; CHECK-NEXT: vdiv.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = sdiv <vscale x 64 x i8> %va, %vb
ret <vscale x 64 x i8> %vc
@@ -261,7 +261,7 @@ define <vscale x 64 x i8> @vdiv_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b
; CHECK-LABEL: vdiv_vx_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
@@ -292,7 +292,7 @@ define <vscale x 1 x i16> @vdiv_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x
; CHECK-LABEL: vdiv_vv_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 1 x i16> %va, %vb
ret <vscale x 1 x i16> %vc
@@ -302,7 +302,7 @@ define <vscale x 1 x i16> @vdiv_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %
; CHECK-LABEL: vdiv_vx_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -333,7 +333,7 @@ define <vscale x 2 x i16> @vdiv_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x
; CHECK-LABEL: vdiv_vv_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 2 x i16> %va, %vb
ret <vscale x 2 x i16> %vc
@@ -343,7 +343,7 @@ define <vscale x 2 x i16> @vdiv_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %
; CHECK-LABEL: vdiv_vx_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -374,7 +374,7 @@ define <vscale x 4 x i16> @vdiv_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x
; CHECK-LABEL: vdiv_vv_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 4 x i16> %va, %vb
ret <vscale x 4 x i16> %vc
@@ -384,7 +384,7 @@ define <vscale x 4 x i16> @vdiv_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %
; CHECK-LABEL: vdiv_vx_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -415,7 +415,7 @@ define <vscale x 8 x i16> @vdiv_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x
; CHECK-LABEL: vdiv_vv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v10
+; CHECK-NEXT: vdiv.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = sdiv <vscale x 8 x i16> %va, %vb
ret <vscale x 8 x i16> %vc
@@ -425,7 +425,7 @@ define <vscale x 8 x i16> @vdiv_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %
; CHECK-LABEL: vdiv_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -456,7 +456,7 @@ define <vscale x 16 x i16> @vdiv_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x
; CHECK-LABEL: vdiv_vv_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v12
+; CHECK-NEXT: vdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = sdiv <vscale x 16 x i16> %va, %vb
ret <vscale x 16 x i16> %vc
@@ -466,7 +466,7 @@ define <vscale x 16 x i16> @vdiv_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signex
; CHECK-LABEL: vdiv_vx_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -497,7 +497,7 @@ define <vscale x 32 x i16> @vdiv_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x
; CHECK-LABEL: vdiv_vv_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v16
+; CHECK-NEXT: vdiv.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = sdiv <vscale x 32 x i16> %va, %vb
ret <vscale x 32 x i16> %vc
@@ -507,7 +507,7 @@ define <vscale x 32 x i16> @vdiv_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signex
; CHECK-LABEL: vdiv_vx_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
@@ -538,7 +538,7 @@ define <vscale x 1 x i32> @vdiv_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x
; CHECK-LABEL: vdiv_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 1 x i32> %va, %vb
ret <vscale x 1 x i32> %vc
@@ -548,7 +548,7 @@ define <vscale x 1 x i32> @vdiv_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %
; CHECK-LABEL: vdiv_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -580,7 +580,7 @@ define <vscale x 2 x i32> @vdiv_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x
; CHECK-LABEL: vdiv_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 2 x i32> %va, %vb
ret <vscale x 2 x i32> %vc
@@ -590,7 +590,7 @@ define <vscale x 2 x i32> @vdiv_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %
; CHECK-LABEL: vdiv_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -622,7 +622,7 @@ define <vscale x 4 x i32> @vdiv_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x
; CHECK-LABEL: vdiv_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v10
+; CHECK-NEXT: vdiv.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = sdiv <vscale x 4 x i32> %va, %vb
ret <vscale x 4 x i32> %vc
@@ -632,7 +632,7 @@ define <vscale x 4 x i32> @vdiv_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %
; CHECK-LABEL: vdiv_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -664,7 +664,7 @@ define <vscale x 8 x i32> @vdiv_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x
; CHECK-LABEL: vdiv_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v12
+; CHECK-NEXT: vdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = sdiv <vscale x 8 x i32> %va, %vb
ret <vscale x 8 x i32> %vc
@@ -674,7 +674,7 @@ define <vscale x 8 x i32> @vdiv_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %
; CHECK-LABEL: vdiv_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -706,7 +706,7 @@ define <vscale x 16 x i32> @vdiv_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x
; CHECK-LABEL: vdiv_vv_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v16
+; CHECK-NEXT: vdiv.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = sdiv <vscale x 16 x i32> %va, %vb
ret <vscale x 16 x i32> %vc
@@ -716,7 +716,7 @@ define <vscale x 16 x i32> @vdiv_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signex
; CHECK-LABEL: vdiv_vx_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
@@ -748,7 +748,7 @@ define <vscale x 1 x i64> @vdiv_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x
; CHECK-LABEL: vdiv_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = sdiv <vscale x 1 x i64> %va, %vb
ret <vscale x 1 x i64> %vc
@@ -758,7 +758,7 @@ define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vdiv_vx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -796,7 +796,7 @@ define <vscale x 2 x i64> @vdiv_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x
; CHECK-LABEL: vdiv_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v10
+; CHECK-NEXT: vdiv.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = sdiv <vscale x 2 x i64> %va, %vb
ret <vscale x 2 x i64> %vc
@@ -806,7 +806,7 @@ define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-LABEL: vdiv_vx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -844,7 +844,7 @@ define <vscale x 4 x i64> @vdiv_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x
; CHECK-LABEL: vdiv_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v12
+; CHECK-NEXT: vdiv.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = sdiv <vscale x 4 x i64> %va, %vb
ret <vscale x 4 x i64> %vc
@@ -854,7 +854,7 @@ define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-LABEL: vdiv_vx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
@@ -892,7 +892,7 @@ define <vscale x 8 x i64> @vdiv_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x
; CHECK-LABEL: vdiv_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT: vdivu.vv v8, v8, v16
+; CHECK-NEXT: vdiv.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = sdiv <vscale x 8 x i64> %va, %vb
ret <vscale x 8 x i64> %vc
@@ -902,7 +902,7 @@ define <vscale x 8 x i64> @vdiv_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; CHECK-LABEL: vdiv_vx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT: vdivu.vx v8, v8, a0
+; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
index 27b27cd64bae..383d3f380fe8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
@@ -5,7 +5,7 @@ define <vscale x 1 x i8> @vdivu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i
; CHECK-LABEL: vdivu_vv_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 1 x i8> %va, %vb
ret <vscale x 1 x i8> %vc
@@ -15,7 +15,7 @@ define <vscale x 1 x i8> @vdivu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b)
; CHECK-LABEL: vdivu_vx_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -68,7 +68,7 @@ define <vscale x 2 x i8> @vdivu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i
; CHECK-LABEL: vdivu_vv_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 2 x i8> %va, %vb
ret <vscale x 2 x i8> %vc
@@ -78,7 +78,7 @@ define <vscale x 2 x i8> @vdivu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b)
; CHECK-LABEL: vdivu_vx_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -107,7 +107,7 @@ define <vscale x 4 x i8> @vdivu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i
; CHECK-LABEL: vdivu_vv_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 4 x i8> %va, %vb
ret <vscale x 4 x i8> %vc
@@ -117,7 +117,7 @@ define <vscale x 4 x i8> @vdivu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b)
; CHECK-LABEL: vdivu_vx_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -146,7 +146,7 @@ define <vscale x 8 x i8> @vdivu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i
; CHECK-LABEL: vdivu_vv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 8 x i8> %va, %vb
ret <vscale x 8 x i8> %vc
@@ -156,7 +156,7 @@ define <vscale x 8 x i8> @vdivu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b)
; CHECK-LABEL: vdivu_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -185,7 +185,7 @@ define <vscale x 16 x i8> @vdivu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16
; CHECK-LABEL: vdivu_vv_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v10
+; CHECK-NEXT: vdivu.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = udiv <vscale x 16 x i8> %va, %vb
ret <vscale x 16 x i8> %vc
@@ -195,7 +195,7 @@ define <vscale x 16 x i8> @vdivu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %
; CHECK-LABEL: vdivu_vx_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -224,7 +224,7 @@ define <vscale x 32 x i8> @vdivu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32
; CHECK-LABEL: vdivu_vv_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v12
+; CHECK-NEXT: vdivu.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = udiv <vscale x 32 x i8> %va, %vb
ret <vscale x 32 x i8> %vc
@@ -234,7 +234,7 @@ define <vscale x 32 x i8> @vdivu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %
; CHECK-LABEL: vdivu_vx_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -263,7 +263,7 @@ define <vscale x 64 x i8> @vdivu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64
; CHECK-LABEL: vdivu_vv_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v16
+; CHECK-NEXT: vdivu.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = udiv <vscale x 64 x i8> %va, %vb
ret <vscale x 64 x i8> %vc
@@ -273,7 +273,7 @@ define <vscale x 64 x i8> @vdivu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %
; CHECK-LABEL: vdivu_vx_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
@@ -302,7 +302,7 @@ define <vscale x 1 x i16> @vdivu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1
; CHECK-LABEL: vdivu_vv_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 1 x i16> %va, %vb
ret <vscale x 1 x i16> %vc
@@ -312,7 +312,7 @@ define <vscale x 1 x i16> @vdivu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext
; CHECK-LABEL: vdivu_vx_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -342,7 +342,7 @@ define <vscale x 2 x i16> @vdivu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2
; CHECK-LABEL: vdivu_vv_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 2 x i16> %va, %vb
ret <vscale x 2 x i16> %vc
@@ -352,7 +352,7 @@ define <vscale x 2 x i16> @vdivu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext
; CHECK-LABEL: vdivu_vx_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -382,7 +382,7 @@ define <vscale x 4 x i16> @vdivu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4
; CHECK-LABEL: vdivu_vv_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 4 x i16> %va, %vb
ret <vscale x 4 x i16> %vc
@@ -392,7 +392,7 @@ define <vscale x 4 x i16> @vdivu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext
; CHECK-LABEL: vdivu_vx_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -422,7 +422,7 @@ define <vscale x 8 x i16> @vdivu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8
; CHECK-LABEL: vdivu_vv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v10
+; CHECK-NEXT: vdivu.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = udiv <vscale x 8 x i16> %va, %vb
ret <vscale x 8 x i16> %vc
@@ -432,7 +432,7 @@ define <vscale x 8 x i16> @vdivu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext
; CHECK-LABEL: vdivu_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -462,7 +462,7 @@ define <vscale x 16 x i16> @vdivu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x
; CHECK-LABEL: vdivu_vv_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v12
+; CHECK-NEXT: vdivu.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = udiv <vscale x 16 x i16> %va, %vb
ret <vscale x 16 x i16> %vc
@@ -472,7 +472,7 @@ define <vscale x 16 x i16> @vdivu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signe
; CHECK-LABEL: vdivu_vx_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -502,7 +502,7 @@ define <vscale x 32 x i16> @vdivu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x
; CHECK-LABEL: vdivu_vv_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v16
+; CHECK-NEXT: vdivu.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = udiv <vscale x 32 x i16> %va, %vb
ret <vscale x 32 x i16> %vc
@@ -512,7 +512,7 @@ define <vscale x 32 x i16> @vdivu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signe
; CHECK-LABEL: vdivu_vx_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
@@ -542,7 +542,7 @@ define <vscale x 1 x i32> @vdivu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1
; CHECK-LABEL: vdivu_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 1 x i32> %va, %vb
ret <vscale x 1 x i32> %vc
@@ -552,7 +552,7 @@ define <vscale x 1 x i32> @vdivu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
; CHECK-LABEL: vdivu_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -582,7 +582,7 @@ define <vscale x 2 x i32> @vdivu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2
; CHECK-LABEL: vdivu_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 2 x i32> %va, %vb
ret <vscale x 2 x i32> %vc
@@ -592,7 +592,7 @@ define <vscale x 2 x i32> @vdivu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
; CHECK-LABEL: vdivu_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -622,7 +622,7 @@ define <vscale x 4 x i32> @vdivu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4
; CHECK-LABEL: vdivu_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v10
+; CHECK-NEXT: vdivu.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = udiv <vscale x 4 x i32> %va, %vb
ret <vscale x 4 x i32> %vc
@@ -632,7 +632,7 @@ define <vscale x 4 x i32> @vdivu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
; CHECK-LABEL: vdivu_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -662,7 +662,7 @@ define <vscale x 8 x i32> @vdivu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8
; CHECK-LABEL: vdivu_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v12
+; CHECK-NEXT: vdivu.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = udiv <vscale x 8 x i32> %va, %vb
ret <vscale x 8 x i32> %vc
@@ -672,7 +672,7 @@ define <vscale x 8 x i32> @vdivu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: vdivu_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -702,7 +702,7 @@ define <vscale x 16 x i32> @vdivu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x
; CHECK-LABEL: vdivu_vv_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v16
+; CHECK-NEXT: vdivu.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = udiv <vscale x 16 x i32> %va, %vb
ret <vscale x 16 x i32> %vc
@@ -712,7 +712,7 @@ define <vscale x 16 x i32> @vdivu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
; CHECK-LABEL: vdivu_vx_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
@@ -742,7 +742,7 @@ define <vscale x 1 x i64> @vdivu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
; CHECK-LABEL: vdivu_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 1 x i64> %va, %vb
ret <vscale x 1 x i64> %vc
@@ -759,7 +759,7 @@ define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-NEXT: vsll.vx v26, v26, a1
; CHECK-NEXT: vsrl.vx v26, v26, a1
; CHECK-NEXT: vor.vv v25, v26, v25
-; CHECK-NEXT: vdiv.vv v8, v8, v25
+; CHECK-NEXT: vdivu.vv v8, v8, v25
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -796,7 +796,7 @@ define <vscale x 2 x i64> @vdivu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
; CHECK-LABEL: vdivu_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v10
+; CHECK-NEXT: vdivu.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = udiv <vscale x 2 x i64> %va, %vb
ret <vscale x 2 x i64> %vc
@@ -813,7 +813,7 @@ define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-NEXT: vsll.vx v28, v28, a1
; CHECK-NEXT: vsrl.vx v28, v28, a1
; CHECK-NEXT: vor.vv v26, v28, v26
-; CHECK-NEXT: vdiv.vv v8, v8, v26
+; CHECK-NEXT: vdivu.vv v8, v8, v26
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -850,7 +850,7 @@ define <vscale x 4 x i64> @vdivu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
; CHECK-LABEL: vdivu_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v12
+; CHECK-NEXT: vdivu.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = udiv <vscale x 4 x i64> %va, %vb
ret <vscale x 4 x i64> %vc
@@ -867,7 +867,7 @@ define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-NEXT: vsll.vx v12, v12, a1
; CHECK-NEXT: vsrl.vx v12, v12, a1
; CHECK-NEXT: vor.vv v28, v12, v28
-; CHECK-NEXT: vdiv.vv v8, v8, v28
+; CHECK-NEXT: vdivu.vv v8, v8, v28
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
@@ -904,7 +904,7 @@ define <vscale x 8 x i64> @vdivu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
; CHECK-LABEL: vdivu_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v16
+; CHECK-NEXT: vdivu.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = udiv <vscale x 8 x i64> %va, %vb
ret <vscale x 8 x i64> %vc
@@ -921,7 +921,7 @@ define <vscale x 8 x i64> @vdivu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; CHECK-NEXT: vsll.vx v24, v24, a1
; CHECK-NEXT: vsrl.vx v24, v24, a1
; CHECK-NEXT: vor.vv v16, v24, v16
-; CHECK-NEXT: vdiv.vv v8, v8, v16
+; CHECK-NEXT: vdivu.vv v8, v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
index 70cd4fba1eb7..bc72099d75eb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
@@ -5,7 +5,7 @@ define <vscale x 1 x i8> @vdivu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i
; CHECK-LABEL: vdivu_vv_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 1 x i8> %va, %vb
ret <vscale x 1 x i8> %vc
@@ -15,7 +15,7 @@ define <vscale x 1 x i8> @vdivu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b)
; CHECK-LABEL: vdivu_vx_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
@@ -44,7 +44,7 @@ define <vscale x 2 x i8> @vdivu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i
; CHECK-LABEL: vdivu_vv_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 2 x i8> %va, %vb
ret <vscale x 2 x i8> %vc
@@ -54,7 +54,7 @@ define <vscale x 2 x i8> @vdivu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b)
; CHECK-LABEL: vdivu_vx_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
@@ -83,7 +83,7 @@ define <vscale x 4 x i8> @vdivu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i
; CHECK-LABEL: vdivu_vv_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 4 x i8> %va, %vb
ret <vscale x 4 x i8> %vc
@@ -93,7 +93,7 @@ define <vscale x 4 x i8> @vdivu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b)
; CHECK-LABEL: vdivu_vx_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
@@ -122,7 +122,7 @@ define <vscale x 8 x i8> @vdivu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i
; CHECK-LABEL: vdivu_vv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 8 x i8> %va, %vb
ret <vscale x 8 x i8> %vc
@@ -132,7 +132,7 @@ define <vscale x 8 x i8> @vdivu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b)
; CHECK-LABEL: vdivu_vx_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -161,7 +161,7 @@ define <vscale x 16 x i8> @vdivu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16
; CHECK-LABEL: vdivu_vv_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v10
+; CHECK-NEXT: vdivu.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = udiv <vscale x 16 x i8> %va, %vb
ret <vscale x 16 x i8> %vc
@@ -171,7 +171,7 @@ define <vscale x 16 x i8> @vdivu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %
; CHECK-LABEL: vdivu_vx_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
@@ -200,7 +200,7 @@ define <vscale x 32 x i8> @vdivu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32
; CHECK-LABEL: vdivu_vv_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v12
+; CHECK-NEXT: vdivu.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = udiv <vscale x 32 x i8> %va, %vb
ret <vscale x 32 x i8> %vc
@@ -210,7 +210,7 @@ define <vscale x 32 x i8> @vdivu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %
; CHECK-LABEL: vdivu_vx_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
@@ -239,7 +239,7 @@ define <vscale x 64 x i8> @vdivu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64
; CHECK-LABEL: vdivu_vv_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v16
+; CHECK-NEXT: vdivu.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = udiv <vscale x 64 x i8> %va, %vb
ret <vscale x 64 x i8> %vc
@@ -249,7 +249,7 @@ define <vscale x 64 x i8> @vdivu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %
; CHECK-LABEL: vdivu_vx_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
@@ -278,7 +278,7 @@ define <vscale x 1 x i16> @vdivu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1
; CHECK-LABEL: vdivu_vv_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 1 x i16> %va, %vb
ret <vscale x 1 x i16> %vc
@@ -288,7 +288,7 @@ define <vscale x 1 x i16> @vdivu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext
; CHECK-LABEL: vdivu_vx_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
@@ -318,7 +318,7 @@ define <vscale x 2 x i16> @vdivu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2
; CHECK-LABEL: vdivu_vv_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 2 x i16> %va, %vb
ret <vscale x 2 x i16> %vc
@@ -328,7 +328,7 @@ define <vscale x 2 x i16> @vdivu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext
; CHECK-LABEL: vdivu_vx_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
@@ -358,7 +358,7 @@ define <vscale x 4 x i16> @vdivu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4
; CHECK-LABEL: vdivu_vv_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 4 x i16> %va, %vb
ret <vscale x 4 x i16> %vc
@@ -368,7 +368,7 @@ define <vscale x 4 x i16> @vdivu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext
; CHECK-LABEL: vdivu_vx_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -398,7 +398,7 @@ define <vscale x 8 x i16> @vdivu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8
; CHECK-LABEL: vdivu_vv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v10
+; CHECK-NEXT: vdivu.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = udiv <vscale x 8 x i16> %va, %vb
ret <vscale x 8 x i16> %vc
@@ -408,7 +408,7 @@ define <vscale x 8 x i16> @vdivu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext
; CHECK-LABEL: vdivu_vx_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@@ -438,7 +438,7 @@ define <vscale x 16 x i16> @vdivu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x
; CHECK-LABEL: vdivu_vv_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v12
+; CHECK-NEXT: vdivu.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = udiv <vscale x 16 x i16> %va, %vb
ret <vscale x 16 x i16> %vc
@@ -448,7 +448,7 @@ define <vscale x 16 x i16> @vdivu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signe
; CHECK-LABEL: vdivu_vx_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
@@ -478,7 +478,7 @@ define <vscale x 32 x i16> @vdivu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x
; CHECK-LABEL: vdivu_vv_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v16
+; CHECK-NEXT: vdivu.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = udiv <vscale x 32 x i16> %va, %vb
ret <vscale x 32 x i16> %vc
@@ -488,7 +488,7 @@ define <vscale x 32 x i16> @vdivu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signe
; CHECK-LABEL: vdivu_vx_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
@@ -518,7 +518,7 @@ define <vscale x 1 x i32> @vdivu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1
; CHECK-LABEL: vdivu_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 1 x i32> %va, %vb
ret <vscale x 1 x i32> %vc
@@ -528,7 +528,7 @@ define <vscale x 1 x i32> @vdivu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext
; CHECK-LABEL: vdivu_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
@@ -558,7 +558,7 @@ define <vscale x 2 x i32> @vdivu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2
; CHECK-LABEL: vdivu_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 2 x i32> %va, %vb
ret <vscale x 2 x i32> %vc
@@ -568,7 +568,7 @@ define <vscale x 2 x i32> @vdivu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext
; CHECK-LABEL: vdivu_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
@@ -598,7 +598,7 @@ define <vscale x 4 x i32> @vdivu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4
; CHECK-LABEL: vdivu_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v10
+; CHECK-NEXT: vdivu.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = udiv <vscale x 4 x i32> %va, %vb
ret <vscale x 4 x i32> %vc
@@ -608,7 +608,7 @@ define <vscale x 4 x i32> @vdivu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext
; CHECK-LABEL: vdivu_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
@@ -638,7 +638,7 @@ define <vscale x 8 x i32> @vdivu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8
; CHECK-LABEL: vdivu_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v12
+; CHECK-NEXT: vdivu.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = udiv <vscale x 8 x i32> %va, %vb
ret <vscale x 8 x i32> %vc
@@ -648,7 +648,7 @@ define <vscale x 8 x i32> @vdivu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext
; CHECK-LABEL: vdivu_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@@ -678,7 +678,7 @@ define <vscale x 16 x i32> @vdivu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x
; CHECK-LABEL: vdivu_vv_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v16
+; CHECK-NEXT: vdivu.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = udiv <vscale x 16 x i32> %va, %vb
ret <vscale x 16 x i32> %vc
@@ -688,7 +688,7 @@ define <vscale x 16 x i32> @vdivu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signe
; CHECK-LABEL: vdivu_vx_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
@@ -718,7 +718,7 @@ define <vscale x 1 x i64> @vdivu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
; CHECK-LABEL: vdivu_vv_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%vc = udiv <vscale x 1 x i64> %va, %vb
ret <vscale x 1 x i64> %vc
@@ -728,7 +728,7 @@ define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vdivu_vx_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
@@ -760,7 +760,7 @@ define <vscale x 2 x i64> @vdivu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
; CHECK-LABEL: vdivu_vv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v10
+; CHECK-NEXT: vdivu.vv v8, v8, v10
; CHECK-NEXT: ret
%vc = udiv <vscale x 2 x i64> %va, %vb
ret <vscale x 2 x i64> %vc
@@ -770,7 +770,7 @@ define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-LABEL: vdivu_vx_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
@@ -802,7 +802,7 @@ define <vscale x 4 x i64> @vdivu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
; CHECK-LABEL: vdivu_vv_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v12
+; CHECK-NEXT: vdivu.vv v8, v8, v12
; CHECK-NEXT: ret
%vc = udiv <vscale x 4 x i64> %va, %vb
ret <vscale x 4 x i64> %vc
@@ -812,7 +812,7 @@ define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-LABEL: vdivu_vx_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
@@ -844,7 +844,7 @@ define <vscale x 8 x i64> @vdivu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
; CHECK-LABEL: vdivu_vv_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT: vdiv.vv v8, v8, v16
+; CHECK-NEXT: vdivu.vv v8, v8, v16
; CHECK-NEXT: ret
%vc = udiv <vscale x 8 x i64> %va, %vb
ret <vscale x 8 x i64> %vc
@@ -854,7 +854,7 @@ define <vscale x 8 x i64> @vdivu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; CHECK-LABEL: vdivu_vx_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT: vdiv.vx v8, v8, a0
+; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
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