[llvm] c4fd198 - [RISCV] Correct types in tablegen multiclasses found by D95874.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-02-02T10:39:47-08:00
New Revision: c4fd1981a74520aaa1731f8705360c2c87346f44

URL: https://github.com/llvm/llvm-project/commit/c4fd1981a74520aaa1731f8705360c2c87346f44
DIFF: https://github.com/llvm/llvm-project/commit/c4fd1981a74520aaa1731f8705360c2c87346f44.diff

LOG: [RISCV] Correct types in tablegen multiclasses found by D95874.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index c246055f40f8..2966c331dca8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -865,7 +865,7 @@ class VPseudoIStoreMask<VReg StClass, VReg IdxClass>:
 }
 
 class VPseudoBinaryMask<VReg RetClass,
-                        VReg Op1Class,
+                        RegisterClass Op1Class,
                         DAGOperand Op2Class,
                         string Constraint> :
         Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
@@ -911,7 +911,7 @@ class VPseudoBinaryCarryIn<VReg RetClass,
 }
 
 class VPseudoTernaryNoMask<VReg RetClass,
-                           VReg Op1Class,
+                           RegisterClass Op1Class,
                            DAGOperand Op2Class,
                            string Constraint> :
         Pseudo<(outs RetClass:$rd),
@@ -1696,8 +1696,8 @@ multiclass VPseudoBinaryV_WV_WX_WI {
 }
 
 multiclass VPseudoTernary<VReg RetClass,
-                          VReg Op1Class,
-                          RegisterClass Op2Class,
+                          RegisterClass Op1Class,
+                          DAGOperand Op2Class,
                           LMULInfo MInfo,
                           string Constraint = ""> {
   let VLMul = MInfo.value in {
@@ -2147,8 +2147,8 @@ class VPatAMOWDMask<string intrinsic_name,
 
 multiclass VPatUSLoad<string intrinsic,
                       string inst,
-                      LLVMType type,
-                      LLVMType mask_type,
+                      ValueType type,
+                      ValueType mask_type,
                       int sew,
                       LMULInfo vlmul,
                       VReg reg_class>
@@ -2166,8 +2166,8 @@ multiclass VPatUSLoad<string intrinsic,
 }
 
 multiclass VPatUSLoadFF<string inst,
-                        LLVMType type,
-                        LLVMType mask_type,
+                        ValueType type,
+                        ValueType mask_type,
                         int sew,
                         LMULInfo vlmul,
                         VReg reg_class>
@@ -2184,8 +2184,8 @@ multiclass VPatUSLoadFF<string inst,
 
 multiclass VPatSLoad<string intrinsic,
                      string inst,
-                     LLVMType type,
-                     LLVMType mask_type,
+                     ValueType type,
+                     ValueType mask_type,
                      int sew,
                      LMULInfo vlmul,
                      VReg reg_class>
@@ -2204,9 +2204,9 @@ multiclass VPatSLoad<string intrinsic,
 
 multiclass VPatILoad<string intrinsic,
                      string inst,
-                     LLVMType type,
-                     LLVMType idx_type,
-                     LLVMType mask_type,
+                     ValueType type,
+                     ValueType idx_type,
+                     ValueType mask_type,
                      int sew,
                      LMULInfo vlmul,
                      LMULInfo idx_vlmul,
@@ -2229,8 +2229,8 @@ multiclass VPatILoad<string intrinsic,
 
 multiclass VPatUSStore<string intrinsic,
                        string inst,
-                       LLVMType type,
-                       LLVMType mask_type,
+                       ValueType type,
+                       ValueType mask_type,
                        int sew,
                        LMULInfo vlmul,
                        VReg reg_class>
@@ -2247,8 +2247,8 @@ multiclass VPatUSStore<string intrinsic,
 
 multiclass VPatSStore<string intrinsic,
                       string inst,
-                      LLVMType type,
-                      LLVMType mask_type,
+                      ValueType type,
+                      ValueType mask_type,
                       int sew,
                       LMULInfo vlmul,
                       VReg reg_class>
@@ -2265,9 +2265,9 @@ multiclass VPatSStore<string intrinsic,
 
 multiclass VPatIStore<string intrinsic,
                       string inst,
-                      LLVMType type,
-                      LLVMType idx_type,
-                      LLVMType mask_type,
+                      ValueType type,
+                      ValueType idx_type,
+                      ValueType mask_type,
                       int sew,
                       LMULInfo vlmul,
                       LMULInfo idx_vlmul,

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index babd9eb43e0a..0ffa022d64d8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -45,8 +45,8 @@ class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
    dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
 }
 
-multiclass VPatUSLoadStoreSDNode<LLVMType type,
-                                 LLVMType mask_type,
+multiclass VPatUSLoadStoreSDNode<ValueType type,
+                                 ValueType mask_type,
                                  int sew,
                                  LMULInfo vlmul,
                                  OutPatFrag avl,