[PATCH] D95861: [AMDGPU] Save fp/bp after csr saves

[Sebastian Neubauer via Phabricator via llvm-commits]

sebastian-ne marked an inline comment as done.
sebastian-ne added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll:600-601
 
+; When flat-scratch is enabled, we save the FP to s0. At the same time,
+; the exec register is saved to s0 when saving CSR in the function prolog.
+; Make sure that the FP save happens after restoring exec from the same
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arsenm wrote:
> How is it saved to s0 when that's reserved for the first register in the scratch SRD?
This is only with flat-scratch instructions enabled, so there is no SRD and s0–s3 are free


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