[PATCH] D95861: [AMDGPU] Save fp/bp after csr saves

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll:600-601
 
+; When flat-scratch is enabled, we save the FP to s0. At the same time,
+; the exec register is saved to s0 when saving CSR in the function prolog.
+; Make sure that the FP save happens after restoring exec from the same
----------------
How is it saved to s0 when that's reserved for the first register in the scratch SRD?


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Comment at: llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll:608
+; FLATSCR: s_mov_b64 exec, s[0:1]
+; FLATSCR: s_mov_b32 s0, s33
+; FLATSCR: s_mov_b32 s33, s32
----------------
This is trashing the SRD


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D95861/new/

https://reviews.llvm.org/D95861