[PATCH] D95781: [RISCV] Add new vector instructions in v0.10.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai updated this revision to Diff 320641.
HsiangKai added a comment.

Add test cases for invalid vsetivli.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95781/new/

https://reviews.llvm.org/D95781

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll
  llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll
  llvm/test/CodeGen/RISCV/vfrec7-rv32.ll
  llvm/test/CodeGen/RISCV/vfrec7-rv64.ll
  llvm/test/CodeGen/RISCV/vfrece7-rv32.ll
  llvm/test/CodeGen/RISCV/vfrece7-rv64.ll
  llvm/test/CodeGen/RISCV/vfrsqrt7-rv32.ll
  llvm/test/CodeGen/RISCV/vfrsqrt7-rv64.ll
  llvm/test/CodeGen/RISCV/vfrsqrte7-rv32.ll
  llvm/test/CodeGen/RISCV/vfrsqrte7-rv64.ll
  llvm/test/MC/RISCV/rvv/fothers.s
  llvm/test/MC/RISCV/rvv/invalid.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/vsetvl.s
  llvm/test/MC/RISCV/rvv/zvlsseg.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D95781.320641.patch
Type: text/x-patch
Size: 288947 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210202/36fba7f1/attachment-0001.bin>