[PATCH] D95781: [RISCV] Add new vector instructions in v0.10.

Zakk Chen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 1 16:23:30 PST 2021

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khchen added a comment.

LGTM.
Do we need to have a test for `vsetivli` in invalid.s?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D95781/new/

https://reviews.llvm.org/D95781

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