[PATCH] D95705: [RISCV] Add initial support for converting fixed vectors to scalable vectors during lowering to use RVV instructions.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:115
+  // Vector binary and unary ops with VL as a third operand.
+  ADD_VL,
+  AND_VL,
----------------
frasercrmck wrote:
> Is this something that is likely to be part of the vector predication support, once that becomes more "first class"?
It looks like the vector predication SD nodes also have a mask operand. So I'm not sure if we should synthesize an all 1s mask to pattern match back out. Or if we should DAG combine an all ones mask on the vector predication SD nodes to these nodes.

It looks like for masking, the vector predication nodes just make the masked out elements undefined, so I think we still need a VSELECT to specify a passthru value? So I'm not sure if we should pattern match that sequence or DAG combine to an ISD node that has the mask, passthru, and VL all together?


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  https://reviews.llvm.org/D95705/new/

https://reviews.llvm.org/D95705