[PATCH] D95705: [RISCV] Add initial support for converting fixed vectors to scalable vectors during lowering to use RVV instructions.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.
Herald added a subscriber: StephenFan.

I think this is a sensible direction to consider. I do think we'll need to think about other LMULs though.

If we know the minimum size, there's presumably a way to successively enable larger vectors as the size increases? Ideally with `vector-bits-min=1024` we'd be able to support e.g. `<16 x i64>` with LMUL=1, with `vector-bits-min=512` we could do it with LMUL=2. Is that going to be challenging?

We might have to limit it somewhat sensibly: for vector types that would require LMUL=8 we're not necessarily going to see a huge difference in performance compared with just splitting the vector in two.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1724
+
+// Grow V to consume an entire SVE register.
+static SDValue convertToScalableVector(EVT VT, SDValue V, SelectionDAG &DAG,
----------------
Copy/paste on `SVE`?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:115
+  // Vector binary and unary ops with VL as a third operand.
+  ADD_VL,
+  AND_VL,
----------------
Is this something that is likely to be part of the vector predication support, once that becomes more "first class"?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95705/new/

https://reviews.llvm.org/D95705