[PATCH] D95774: [RISCV] Optimize (srl (and X, 0xffff), C) -> (srli (slli X, 16), 16 + C).

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D95774#2533472 <https://reviews.llvm.org/D95774#2533472>, @frasercrmck wrote:

> Looks good, but I'm wondering if this is already a target-independent transform (depending on the cost to materialize the constant)? If not, why not?

There is a transform to swap the srl+and to and+srl in DAGCombiner::visitShiftByConstant but its pretty restrictive about when it fires. I didn't find one turn srl+and into a pair of shifts. We do have the opposite transform to turn a pair of shifts into a shift+and which can be disabled with shouldFoldConstantShiftPairToMask. ARM has CombineANDShift which handles and+shl/shr by turning it into a shift pair. The shouldFoldConstantShiftPairToMask hook was added along with it.


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