[PATCH] D95610: [AMDGPU] Clarify calling conv about inactive lanes

[Tony Tye via Phabricator via llvm-commits]

t-tye added inline comments.


================
Comment at: llvm/docs/AMDGPUUsage.rst:8261
+          registers are intermixed at regular intervals in order to keep a
+          similar ratio independent of the amount of allocated VGPRs.
+
----------------
the number of


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  https://reviews.llvm.org/D95610/new/

https://reviews.llvm.org/D95610