[PATCH] D95781: [RISCV] Add new vector instructions in v0.10.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll:19
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mv a0, zero
-; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vsetivli a0, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    ret
----------------
`zero` is alias of `x0`, so I think here should be `0` rather than `zero`.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll:28
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mv a0, zero
-; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vsetivli a0, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    ret
----------------
Ditto.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95781/new/

https://reviews.llvm.org/D95781