[PATCH] D95781: [RISCV] Add new vector instructions in v0.10.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
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Add new vector instructions in v0.10.

- load/store for mask value

vle1.v
vse1.v

- vsetivli for 0-31 immediate vector length.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95781

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll
  llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll
  llvm/test/CodeGen/RISCV/vfrec7-rv32.ll
  llvm/test/CodeGen/RISCV/vfrec7-rv64.ll
  llvm/test/CodeGen/RISCV/vfrece7-rv32.ll
  llvm/test/CodeGen/RISCV/vfrece7-rv64.ll
  llvm/test/CodeGen/RISCV/vfrsqrt7-rv32.ll
  llvm/test/CodeGen/RISCV/vfrsqrt7-rv64.ll
  llvm/test/CodeGen/RISCV/vfrsqrte7-rv32.ll
  llvm/test/CodeGen/RISCV/vfrsqrte7-rv64.ll
  llvm/test/MC/RISCV/rvv/fothers.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/vsetvl.s
  llvm/test/MC/RISCV/rvv/zvlsseg.s

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